学堂在线清华大学数字集成电路分析与设计(2021春)课后作业题答案
- Dynamic networks with low swing pre-charged nodes, located in adjacenc 2021-05-27
- Interconnect parasitics reduce robustness and power dissipation. A) Tr 2021-05-27
- Mark out all the correct statements about the way to cope with crossta 2021-05-27
- To minimize the resistance of the wires, it is desirable to keep the c 2021-05-27
- Mark out all the correct statements about the interconnect parasitics. 2021-05-27
- Mark out all the correct statements about the distributed rc line. A) 2021-05-27
- Silicide can be used to reduce the sheet resistance of polysilicon. A) 2021-05-27
- The area of logarithmic shifter is dominated by wiring while that of b 2021-05-27
- It’s important to optimize the SUM and CARRY delays with similar valu 2021-05-27
- Mirror adder has a similar value for sum and carry delays. A) True B) 2021-05-27
- For an N-bit ripple-carry adder, it’s far more important to optimize 2021-05-27
- Which one in the following is the correct expression for “carry delet 2021-05-27
- Which one in the following belongs to arithmetic unit? (Mark out all t 2021-05-27
- Which one in the following is part of a generic digital processor? (Ma 2021-05-27
- Mark out all the correct statements about true single phase clocked re 2021-05-27
- As for C2MOS, clock overlap could activate PDN or PUN of a latch but n 2021-05-27
- As shown in Fig. 1, “D” must be stable during 0-0 clock overlap. A 2021-05-27
- Adding a week feedback inverter to a dynamic latch can improve the noi 2021-05-27
- Mark out all the correct statements about the dynamic latch. A) It’s 2021-05-27
- The master latch of the negative edge-triggered register is? A) Negati 2021-05-27
- Tcdreg means the propagation delay in the best case. A) True B) False 2021-05-27
- Mark out all the correct statements about the static memory. A) Not se 2021-05-27
- Only 1->0 transitions are allowed at inputs of PUN. A) True B) False 2021-05-27
- Only inverting logic can be implemented with Domino Logic. A) True B) 2021-05-27
- Mark out all the correct statements about the dynamic CMOS A) Reduced 2021-05-27
